Senior Digital Engineer

Morse Micro

Sydney

3 weeks ago

Sydney

3 weeks ago

Apply

Senior Digital Engineer

Morse Micro is seeking a Senior Digital Engineer to design next-generation Wi-Fi chips for IoT. The role involves SystemVerilog/Chisel RTL design, verification, low-power techniques, and AI tool adoption. Requires 5+ years experience, relocation and visa support available.

Apply

On-site

Full-time

Senior

SystemVerilog

Chisel

Salary

Not specified

Work Location

Sydney, New South Wales, Australia, AU

Work Model

On-site

Experience Required

5 years

Employment Type

Full-time

Experience Level

Senior

Core Qualifications

Technical (Must-have)

SystemVerilogChiselVerilogC programmingPythonTclShellMakefilesCDC/RDC analysislow-power design techniques

Soft Skills

communicationteamworkproblem solvinganalyticaldeterminationhands-on attitude

Preferred Qualifications

Technical (Nice-to-have)

experience with design automation and infrastructure developmentknowledge of low-power design techniquesfamiliarity with embedded systems, bus or processor architectures

Key Responsibilities

•Deliver SystemVerilog and Chisel RTL across chip, subsystem, and block levels, meeting PPA targets.
•Own microarchitecture and design specifications for chip-, subsystem-, and block-level digital logic.
•Drive verification strategy and test plan closure (RTL sims, GLS, X-prop, CDC/RDC, lint, FPGA emulation) through our phase-gate methodology.
•Derive product, subsystem, and block-level feature and performance requirements by studying competitor parts, tracking state of the art in low-power wireless/IoT SoCs, and translating market direction into technical specifications.
•Enhance and maintain our digital design and verification infrastructure.
•Architect clocking, reset, and power domains; author and close UPF/CPF power intent through to GLS and PA simulation.
•Apply low-power techniques (clock gating, power gating, retention, isolation) appropriate to battery- and energy-harvesting IoT applications.
•Integrate mixed-signal IP (ADPLL, PHY, pads, analog macros) and own the digital/analog interface contract.
•Partner with firmware and PHY/MAC teams on register interfaces, programming models, interrupts, and boot sequences to enable efficient HW/SW co-design.
•Take on chip-lead duties: drive system verification, synthesis QoR, P&R support, gate-level netlist and power-aware sims, ECO and LEC closure, and tapeout checklist completion.
•Coordinate across analog, layout, PnR, DFT, and SW teams to hit major project milestones.
•Use AI coding assistants and agents fluently across RTL, verification, scripting, and documentation tasks, with sound judgement on where they accelerate work and where they need close review.
•Identify opportunities to apply AI to our design and verification flows — spec analysis, test generation, debug, code review, infrastructure automation — and drive their adoption across the team.
•Deliver large, complex projects on schedule with multiple concurrent spins.
•Mentor junior team members and uphold design quality through reviews, coding standards, and methodology improvements.

Senior Digital EngineerSemiconductorWi-FiIoTSystemVerilogChiselRTL designlow-powerSydneyfull-time

Key Responsibilities

•Deliver SystemVerilog and Chisel RTL across chip, subsystem, and block levels, meeting PPA targets.

•Own microarchitecture and design specifications for chip-, subsystem-, and block-level digital logic.

•Drive verification strategy and test plan closure (RTL sims, GLS, X-prop, CDC/RDC, lint, FPGA emulation) through our phase-gate methodology.

•Derive product, subsystem, and block-level feature and performance requirements by studying competitor parts, tracking state of the art in low-power wireless/IoT SoCs, and translating market direction into technical specifications.

•Enhance and maintain our digital design and verification infrastructure.

•Architect clocking, reset, and power domains; author and close UPF/CPF power intent through to GLS and PA simulation.

•Apply low-power techniques (clock gating, power gating, retention, isolation) appropriate to battery- and energy-harvesting IoT applications.

•Integrate mixed-signal IP (ADPLL, PHY, pads, analog macros) and own the digital/analog interface contract.

•Partner with firmware and PHY/MAC teams on register interfaces, programming models, interrupts, and boot sequences to enable efficient HW/SW co-design.

•Take on chip-lead duties: drive system verification, synthesis QoR, P&R support, gate-level netlist and power-aware sims, ECO and LEC closure, and tapeout checklist completion.

•Coordinate across analog, layout, PnR, DFT, and SW teams to hit major project milestones.

•Use AI coding assistants and agents fluently across RTL, verification, scripting, and documentation tasks, with sound judgement on where they accelerate work and where they need close review.

•Identify opportunities to apply AI to our design and verification flows — spec analysis, test generation, debug, code review, infrastructure automation — and drive their adoption across the team.

•Deliver large, complex projects on schedule with multiple concurrent spins.

•Mentor junior team members and uphold design quality through reviews, coding standards, and methodology improvements.